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the information in this document is subject to change without notice. before using this document, please confirm that this is the latest version. not all products and/or types are available in every country. please check with an nec electronics sales representative for availability and additional information. mos integrated circuit pd720101 usb2.0 host controller document no. s16265ej4v0ds00 (4th edition) date published june 2004 ns cp (n) printed in japan data sheet the mark shows major revised points. 2002 the pd720101 complies with the universal serial bus s pecification revision 2.0 and open host controller interface specification for full-/low-speed signaling and inte l's enhanced host controller in terface specification for high-speed signaling and works up to 480 mbps. the pd720101 is integrated 3 host controller cores with pci interface and usb2.0 transceivers into a single chip. detailed function descriptions are provided in the following user?s manual. be sure to read the manual before designing. pd720101 user?s manual: s16336e features ? compliant with universal serial bus specif ication revision 2.0 (dat a rate 1.5/12/480 mbps) ? compliant with open host controller in terface specification for usb rev 1.0a ? compliant with enhanced host controller interface specification for usb rev 1.0 ? pci multi-function device consists of two ohci host controller cores for full-/low-speed signaling and one ehci host controller core for high-speed signaling. ? root hub with 5 (max.) downstream facing ports which are shared by ohci and ehci host controller cores. ? all downstream facing ports can handle high-speed (480 m bps), full-speed (12 mbps), and low-speed (1.5 mbps) transaction. ? configurable number of downstream facing ports (2 to 5) ? 32-bit 33 mhz host interface compliant to pci specification release 2.2 ? supports pci mobile design guide revision 1.1 ? supports pci-bus power management in terface specificat ion release 1.1 ? pci bus bus-master access ? system clock is generated by 30 mhz x?tal or 48 mhz clock input. ? system clock frequency should be set from system software (bios) or eeprom. more detail, see pd720101 user?s manual. ? operational registers direct-mapped to pci memory space ? legacy support for all downstream facing ports. legacy s upport features allow easy migration for motherboard implementation. ? 3.3 v power supply, pci signal pins have 5 v tolerant circuit. ordering information part number package pd720101gj-uen 144-pin plastic lqfp (fine pitch) (20 20) pd720101f1-ea8 144-pin plastic fbga (12 12)
data sheet s16265ej4v0ds 2 pd720101 block diagram intb0 pci bus pci bus interface arbiter ohci host controller #1 ohci host controller #2 ehci host controller root hub phy usb bus port 1 port 2 port 3 port 4 port 5 pme0 wakeup_event wakeup_event wakeup_event inta0 intc0 smi0 remark intb0/intc0 can be shared with inta0 through bios setting. (planning)
data sheet s16265ej4v0ds 3 pd720101 pci bus interface : handles 32-bit 33 mhz pci bus master and target function which comply with pci specification release 2.2. th e number of enabled ports is set by bit in configuration space. arbiter : arbitrates among two ohci host cont roller cores and one ehci host controller core. ohci host controller #1 : handles full- (12 mbps)/ low-speed (1.5 mbps) signaling at port 1, 3, and 5. ohci host controller #2 : handles full- (12 mbps )/low-speed (1.5 mbps) signaling at port 2 and 4. ehci host controller : handles high- (480 mb ps) signaling at port 1, 2, 3, 4, and 5. root hub : handles usb hub function in host cont roller and controls connection (routing) between host controller core and port. phy : consists of high-speed transceiver, full-/low-speed transceiver, serializer, deserializer, etc. inta0 : is the pci interrupt signal for ohci host controller #1. intb0 : is the pci interrupt signal for ohci host controller #2. intc0 : is the pci interrupt sign al for ehci host controller. smi0 : is the interrupt signal which is specifi ed by open host controller interface specification for usb rev 1.0a and enhanced host controlle r interface specification rev 1.0. the smi signal of each ohci host controller and ehci host controller appears at this signal. pme0 : is the interrupt signal which is spec ified by pci-bus power management interface specification release 1.1. wakeup signal of each host controller core appears at this signal. comparison with the pd720100a pd720100a pd720101 (2nd generation) ehci revision 0.95 1.0 ehci 1 1 ohci 2 2 legacy support parallel irq out support no parallel irq support clock 48 mhz osc or 30 mhz osc/x?tal 48 mhz osc or 30 mhz x?tal package 176-pin bga (fp) or 160-pin lqfp 144-pin bga (fp) or 144-pin lqfp
data sheet s16265ej4v0ds 4 pd720101 pin configuration ? 144-pin plastic lqfp (fine pitch) (20 20) pd720101gj-uen top view v dd v dd ntest1 nandtest test xt1/sclk xt2 legc vccrst0 smi0 pme0 pclk vbbrst0 v dd v ss v dd_pci inta0 intb0 intc0 gnt0 req0 ad31 ad30 v ss ad29 ad28 ad27 ad26 ad25 ad24 cbe30 idsel v dd v ss v ss v ss rsdm1 dm1 v dd dp1 rsdp1 v ss rsdm2 dm2 v dd dp2 rsdp2 v ss v dd v ss rsdm3 dm3 v dd dp3 rsdp3 v ss rsdm4 dm4 v dd dp4 rsdp4 v ss v ss v ss v ss v ss ad7 cbe00 ad8 ad9 ad10 ad11 ad12 v dd ad13 ad14 ad15 v ss cbe10 par serr0 perr0 stop0 v dd_pci devsel0 trdy0 irdy0 frame0 cbe20 ad16 ad17 ad18 v dd ad19 ad20 ad21 ad22 smc ad23 v ss v ss v dd av dd av dd rref n.c. n.c. av ss av ss av ss (r) rsdp5 dp5 v dd dm5 rsdm5 v ss ppon5 teb ppon4 ppon3 ppon2 v ss v dd oci3 amc oci4 oci2 oci5 ppon1 oci1 srmod srclk srdta v dd_pci crun0 ad0 ad1 ad2 ad3 ad4 ad5 ad6 v dd v dd 1 5 10 15 20 25 35 30 40 50 55 45 60 65 70 85 90 75 80 95 100 105 110 115 130 135 144 120 125 140
data sheet s16265ej4v0ds 5 pd720101 pin no. pin name pin no. pin name pin no. pin name pin no. pin name 1 v dd 37 v ss 73 v dd 109 v ss 2 v dd 38 v ss 74 v dd 110 v ss 3 oci1 39 ad23 75 ad6 111 rsdm1 4 ppon1 40 ad22 76 ad5 112 dm1 5 oci2 41 ad21 77 ad4 113 v dd 6 ppon2 42 ad20 78 ad3 114 dp1 7 oci3 43 v dd 79 ad2 115 rsdp1 8 ppon3 44 ad19 80 v dd_pci 116 v ss 9 oci4 45 ad18 81 ad1 117 rsdm2 10 ppon4 46 ad17 82 ad0 118 dm2 11 oci5 47 ad16 83 crun0 119 v dd 12 ppon5 48 cbe20 84 n.c. 120 dp2 13 vccrst0 49 frame0 85 n.c. 121 rsdp2 14 pme0 50 irdy0 86 smi0 122 v ss 15 pclk 51 trdy0 87 amc 123 v ss 16 vbbrst0 52 devsel0 88 teb 124 v dd 17 v dd_pci 53 stop0 89 smc 125 v ss 18 v ss 54 v ss 90 legc 126 rsdm3 19 v dd 55 v dd 91 test 127 dm3 20 inta0 56 v dd_pci 92 ntest1 128 v dd 21 intb0 57 perr0 93 v dd 129 dp3 22 intc0 58 serr0 94 xt2 130 rsdp3 23 gnt0 59 par 95 xt1/sclk 131 v ss 24 req0 60 cbe10 96 srclk 132 rsdm4 25 ad31 61 ad15 97 srmod 133 dm4 26 ad30 62 ad14 98 srdta 134 v dd 27 ad29 63 ad13 99 nandtest 135 dp4 28 ad28 64 ad12 100 v ss 136 rsdp4 29 ad27 65 ad11 101 v ss 137 v ss 30 ad26 66 ad10 102 av dd 138 rsdm5 31 ad25 67 ad9 103 rref 139 dm5 32 ad24 68 ad8 104 av ss (r) 140 v dd 33 cbe30 69 cbe00 105 av ss 141 dp5 34 idsel 70 ad7 106 av dd 142 rsdp5 35 v ss 71 v ss 107 av ss 143 v ss 36 v dd 72 v ss 108 v dd 144 v ss remark av ss (r) should be used to connect rref through 1 % precision reference resistor of 9.1 k ? . pins 84 and 85 must be clamped high on the board.
data sheet s16265ej4v0ds 6 pd720101 ? 144-pin plastic fbga (12 12) pd720101f1-ea8 bottom view 25 26 27 28 29 30 31 32 33 34 35 36 14 24 71 72 73 74 75 76 77 78 79 80 81 82 37 13 23 70 111 112 113 114 115 116 117 118 119 120 83 38 12 22 69 110 137 138 139 140 121 84 39 11 21 68 109 122 85 40 10 20 67 108 136 141 123 86 41 9 19 66 107 135 142 124 87 42 8 18 65 106 134 143 125 88 43 7 17 64 105 133 144 126 89 44 6 16 63 104 127 90 45 5 15 62 103 132 131 130 129 128 91 46 4 14 61 102 101 100 99 98 97 96 95 94 93 92 47 3 13 60 59 58 57 56 55 54 53 52 51 50 49 48 2 12 11 10 9 8 7 6 5 4 3 2 1 1 p n m l k j h g f e d c b a
data sheet s16265ej4v0ds 7 pd720101 pin no. pin name pin no. pin name pin no. pin name pin no. pin name 1 v ss 37 v dd 73 v dd 109 nandtest 2 ad23 38 v dd 74 rsdp1 110 v ss 3 ad20 39 ppon2 75 v dd 111 av ss 4 ad18 40 oci4 76 v dd 112 v ss 5 cbe20 41 ppon5 77 dp3 113 dm2 6 trdy0 42 pclk 78 v dd 114 rsdp2 7 serr0 43 intc0 79 rsdm5 115 v ss 8 ad15 44 ad31 80 v dd 116 v dd 9 ad12 45 ad28 81 dp5 117 rsdm4 10 ad9 46 ad25 82 v ss 118 dp4 11 ad7 47 v dd 83 oci1 119 v ss 12 v ss 48 v ss 84 oci2 120 ppon1 13 v dd 49 v ss 85 oci3 121 ppon3 14 v dd 50 ad22 86 oci5 122 ppon4 15 ad3 51 ad21 87 vbbrst0 123 vccrst0 16 ad1 52 v dd 88 intb0 124 v dd_pci 17 n.c. 53 ad16 89 ad30 125 inta0 18 amc 54 devsel0 90 ad26 126 req0 19 xt2 55 perr0 91 ad24 127 ad29 20 srmod 56 ad14 92 idsel 128 ad27 21 v ss 57 ad10 93 cbe30 129 irdy0 22 rref 58 ad8 94 ad19 130 v ss 23 v dd 59 cbe00 95 ad17 131 v dd 24 av ss 60 v ss 96 frame0 132 par 25 v ss 61 ad6 97 stop0 133 smi0 26 rsdm1 62 ad4 98 v dd_pci 134 legc 27 dp1 63 ad2 99 cbe10 135 test 28 rsdm2 64 crun0 100 ad13 136 xt1/sclk 29 dp2 65 teb 101 ad11 137 v ss 30 v ss 66 v dd 102 ad5 138 rsdm3 31 rsdp3 67 srdta 103 v dd_pci 139 dm3 32 dm4 68 av dd 104 ad0 140 v ss 33 rsdp4 69 av ss (r) 105 n.c. 141 pme0 34 dm5 70 av dd 106 smc 142 v ss 35 rsdp5 71 v ss 107 ntest1 143 v dd 36 v ss 72 dm1 108 srclk 144 gnt0 remark av ss (r) should be used to connect rref through 1 % precision reference resistor of 9.1 k ? . pins 17 and 105 must be clamped high on the board.
data sheet s16265ej4v0ds 8 pd720101 1. pin information (1/2) pin name i/o buffer type active level function ad (31 : 0) i/o 5 v pci i/o pci ?ad [31 : 0]? signal cbe (3 : 0)0 i/o 5 v pci i/o pci ?c/be [3 : 0]? signal par i/o 5 v pci i/o pci ?par? signal frame0 i/o 5 v pci i/o pci ?frame#? signal irdy0 i/o 5 v pci i/o pci ?irdy#? signal trdy0 i/o 5 v pci i/o pci ?trdy#? signal stop0 i/o 5 v pci i/o pci ?stop#? signal idsel i 5 v pci input pci ?idsel? signal devsel0 i/o 5 v pci i/o pci ?devsel#? signal req0 o 5 v pci output pci ?req#? signal gnt0 i 5 v pci input pci ?gnt#? signal perr0 i/o 5 v pci i/o pci ?perr#? signal serr0 o 5 v pci n-ch open drain pci ?serr#? signal inta0 o 5 v pci n-ch open drain low pci ?inta#? signal intb0 o 5 v pci n-ch open drain low pci ?intb#? signal intc0 o 5 v pci n-ch open drain low pci ?intc#? signal pclk i 5 v pci input pci ?clk? signal vbbrst0 i 5 v tolerant input low hardware reset for chip crun0 i/o 5 v pci i/o pci ?clkrun#? signal pme0 o 5 v pci n-ch open drain low pci ?pme#? signal vccrst0 i 5 v tolerant input low reset for power management smi0 o 5 v tolerant n-ch open drain low system management interrupt output xt1/sclk i input system clock input or oscillator in xt2 o output oscillator out dp (5 : 1) i/o usb high speed d + i/o usb high speed d + signal dm (5 : 1) i/o usb high speed d ? i/o usb high speed d ? signal rsdp (5 : 1) o usb full speed d + output usb full speed d + signal rsdm (5 : 1) o usb full speed d ? output usb full speed d ? signal oci (5 : 1) i (i/o) input low usb root hub port?s overcurrent status input ppon (5 : 1) o (i/o) output high usb root hub port?s power supply control output legc i (i/o) input high legacy support switch srclk o output serial rom clock out srdta i/o i/o serial rom data srmod i input with 50 k ? pull down r high serial rom input enable rref a analog reference resistor ntest1 i input with 12 k ? pull down r high test pin
data sheet s16265ej4v0ds 9 pd720101 (2/2) pin name i/o buffer type active level function smc i input with 50 k ? pull down r high scan mode control teb i input with 50 k ? pull down r high bist enable amc i input with 50 k ? pull down r high atg mode control test i input with 50 k ? pull down r high test control nandtest i input with 50 k ? pull down r high nand tree test enable av dd v dd for analog circuit v dd v dd v dd_pci 5 v (5 v pci) or 3.3 v (3.3 v pci) av ss v ss for analog circuit v ss v ss n.c. no connection remarks 1. ?5 v tolerant? means that the buffer is 3 v buffer with 5 v tolerant circuit. 2. ?5 v pci? indicates a pci buffer, which complies with the 3 v pci standard, has a 5 v tolerant circuit. it does not indicate that this buffer fully complies wi th 5 v pci standard. however, this function can be used for evaluating the operation of a device on a 5 v add-in card. 3. the signal marked as ?(i/o)? in the above table operates as i/o signals du ring testing. however, they do not need to be considered in normal use.
data sheet s16265ej4v0ds 10 pd720101 2. how to connect to external elements 2.1 handling unused pins to realize less than 5 ports host contro ller implementation, appropriate value shall be set to port no field in ext1 register. and unused pins shall be connected as shown below. pin direction connection method dpx i/o tied to "low". dmx i/o tied to "low". rsdpx o no connection (open) rsdmx o no connection (open) ocix i ?h? clamp pponx o no connection (open) 2.2 usb port connection figure 2-1. usb downstream port connection inside-package dp dm rsdp rsdm r s = 36 ? 1% 15 k ? 5% port: d+ outside-package port: d- r s + r on (resistance for driver which is active) = 45 ? 10% ground r s = 36 ? 1%
data sheet s16265ej4v0ds 11 pd720101 2.3 pll capacitor connection figure 2-2. rref connection inside-package av ss (r) rref 9.1 k ? 1% outside-package 2.4 x?tal connection figure 2-3. x?tal connection inside-package xt1/sclk v ss xt2 outside-package v ss c1 x'tal c2 r the following crystals are evaluated on our reference de sign board. table 2-1 shows the external parameters.
data sheet s16265ej4v0ds 12 pd720101 table 2-1. external parameters vender x?tal r c1 c2 kds note 1 at-49 30.000 mhz 100 ? 12 pf 10 pf ndk note 2 at-41 30.000 mhz 100 ? 10 pf 10 pf at-41cd2 30.000 mhz 100 ? 10 pf 10 pf nx3225da 30.000 mhz 100 ? 10 pf 10 pf nx5032ga 30.000 mhz 100 ? 10 pf 10 pf nx8045gb 30.000 mhz 100 ? 10 pf 10 pf notes 1. daishinku corp. 2. nihon dempa kogyo co., ltd. in using these crystals, contact kds or ndk to get th e specification on external components to be used in conjunction with the crystal. kds's home page: http://www.kdsj.co.jp ndk's home page: http://www.ndk-j.co.jp 2.5 external serial rom connection figure 2-4. external serial rom connection srclk srdta 1.5 k ? external serial rom 3.3 v scl sda a 1 srmod a 0 a 2 gnd v dd wp inside-package outside-package c these pins for external serial rom can be opened, when serial rom is not necessary on board.
data sheet s16265ej4v0ds 13 pd720101 3. electrical specifications 3.1 buffer list ? 3 v input buffer with pull down resistor ntest1, test, srmod, nandtest, smc, amc, teb ? 3 v pci i ol = 9 ma 3-state output buffer ppon(5:1), srclk ? 3 v i ol = 9 ma bi-directional buffer legc, srdta ? 3 v i ol = 9 ma bi-directional buffer with enable (or type) oci(5:1) ? 3 v oscillator interface xt1/sclk, xt2 ? 5 v input buffer vbbrst0, vccrst0 ? 5 v i ol = 12 ma n-ch open drain buffer smi0, pme0, inta0, intb0, intc0, serr0 ? 5 v pci input buffer with enable (or type) pclk, gnt0, idsel ? 5 v pci i ol = 12 ma 3-state output buffer req0 ? 5 v pci i ol = 9 ma bi-directional buffer with input enable (or-type) ad(31:0), cbe(3:0)0, par, frame0, irdy0, trdy0, stop0, devsel0, perr0, crun0 ? usb interface, analog signal dp(5:1), dm(5:1), rsdp (5:1), rsdm(5:1), rref above, ?5 v? refers to a 3 v buffer with 5 v tolerant circuit. therefore, it is possible to have a 5 v connection for an external bus, but the output level will be only up to 3 v, which is the v dd voltage. similarly, ?5 v pci? above refers to a pci buffer that has a 5 v tolerant circuit, which meets the 3 v pci standard; it does not refer to a pci buffer that meets the 5 v pci standard.
data sheet s16265ej4v0ds 14 pd720101 3.2 terminology terms used in absolute maximum ratings parameter symbol meaning power supply voltage v dd , av dd , v dd_pci indicates voltage range within which damage or reduced reliability will not result when power is applied to a v dd pin. input voltage v i indicates voltage range within which damage or reduced reliability will not result when power is applied to an input pin. output voltage v o indicates voltage range within which damage or reduced reliability will not result when power is applied to an output pin. operating ambient temperature t a indicates the ambient temperatur e range for normal logic operations. storage temperature t stg indicates the element temperature range within which damage or reduced reliability will not result while no voltage or current are applied to the device. terms used in recommended operating range parameter symbol meaning power supply voltage v dd , av dd , v dd_pci indicates the voltage range for normal logic operations occur when v ss = 0 v. high-level input voltage v ih indicates the voltage, which is applied to the input pins of the device, is the voltage indicates that the high level states for normal operation of the input buffer. * if a voltage that is equal to or greater than the ?min.? value is applied, the input voltage is guaranteed as high level voltage. low-level input voltage v il indicates the voltage, which is applied to the input pins of the device, is the voltage indicates that the low level states for normal operation of the input buffer. * if a voltage that is equal to or lesser than the ?max.? value is applied, the input voltage is guaranteed as low level voltage. terms used in dc characteristics parameter symbol meaning off-state output leakage current i oz indicates the current that flows from the power supply pins when the rated power supply voltage is applied when a 3-state output has high impedance. output short circuit current i os indicates the current that flows when the output pin is shorted (to gnd pins) when output is at high-level. input leakage current i i indicates the current that flows when the input voltage is supplied to the input pin. low-level output current i ol indicates the current that flows to the output pins when the rated low-level output voltage is being applied. high-level output current i oh indicates the current that flows from the output pins when the rated high- level output voltage is being applied.
data sheet s16265ej4v0ds 15 pd720101 3.3 electrical specifications absolute maximum ratings parameter symbol condition rating unit power supply voltage v dd ? 0.5 to + 4.6 v av dd ? 0.5 to + 4.6 v v dd_pci ? 0.5 to + 6.0 v input voltage, 5 v buffer v i 3.0 v v dd 3.6 v v i < v dd + 3.0 v ? 0.5 to + 6.6 v input voltage, 3.3 v buffer v i 3.0 v v dd 3.6 v v i < v dd + 0.5 v ? 0.5 to + 4.6 v output voltage, 5 v buffer v o 3.0 v v dd 3.6 v v o < v dd + 3.0 v ? 0.5 to + 6.6 v output voltage, 3.3 v buffer v o 3.0 v v dd 3.6 v v o < v dd + 0.5 v ? 0.5 to + 4.6 v operating ambient temperature t a 0 to + 70 c storage temperature t stg ? 65 to + 150 c caution product quality may suffer if the absolute maximum rating is exceeded even momentarily for any parameters. that is, the absolute maximum ratings are rated values at which the product is on the verge of suffering physical damage, and therefore the product must be used under conditions that ensure that the absolute maximum ratings are not exceeded. the ratings and conditions indicated for dc ch aracteristics and ac characteristics represent the quality assurance range during normal operation. recommended operating ranges parameter symbol condition min. typ. max. unit operating voltage v dd 3.0 3.3 3.6 v av dd 3.0 3.3 3.6 v v dd_pci in 3.3 v pci 3.0 3.3 3.6 v in 5 v pci 4.75 5.0 5.25 v high-level input voltage v ih 3.3 v high-level input voltage 2.0 v dd v 5.0 v high-level input voltage 2.0 5.5 v low-level input voltage v il 3.3 v low-level input voltage 0 0.8 v 5.0 v low-level input voltage 0 0.8 v
data sheet s16265ej4v0ds 16 pd720101 dc characteristics (v dd = 3.0 to 3.6 v, t a = 0 to + 70 c) control pin block parameter symbol condition min. max. unit off-state output current i oz v o = v dd or v ss 10 a output short circuit current i os note ? 250 ma low-level output current i ol 3.3 v low-level output current v ol = 0.4 v 9.0 ma 3.3 v low-level output current v ol = 0.4 v 3.0 ma 5.0 v low-level output current v ol = 0.4 v 12.0 ma 5.0 v low-level output current v ol = 0.4 v 6.0 ma high-level output current i oh 3.3 v high-level output current v oh = 2.4 v ? 9.0 ma 3.3 v high-level output current v oh = 2.4 v ? 3.0 ma 5.0 v high-level output current v oh = 2.4 v ? 2.0 ma 5.0 v high-level output current v oh = 2.4 v ? 2.0 ma input leakage current i i 3.3 v buffer v i = v dd or v ss 10 a 3.3 v buffer with 50 k ? pd v i = v dd 191 a 5.0 v buffer v i = v dd or v ss 10 a note the output short circuit time is one second or less and is only for one pin on the lsi. pci interface block parameter symbol condition min. max. unit high-level input voltage v ih 2.0 5.25 v low-level input voltage v il 0 0.8 v low-level output current i ol v ol = 0.4 v 12.0 ma high-level output current i oh v oh = 2.4 v ? 2.0 ma input high leakage current i ih v in = 2.7 v 70 a input low leakage current i il v in = 0.5 v ? 70 a pme0 leakage current i off v o < 3.6 v v cc off or floating 1 a
data sheet s16265ej4v0ds 17 pd720101 usb interface block parameter symbol conditions min. max. unit serial resistor between dp (dm) and rsdp (rsdm) r s 35.64 36.36 ? output pin impedance z hsdrv includes r s resistor 40.5 49.5 ? input levels for low-/full-speed: high-level input voltage (drive) v ih 2.0 v high-level input voltage (floating) v ihz 2.7 3.6 v low-level input voltage v il 0.8 v differential input sensitivity v di ? (d + ) ? (d ? ) ? 0.2 v differential common mode range v cm includes v di range 0.8 2.5 v output levels for low-/full-speed: high-level output voltage v oh r l of 14.25 k ? to gnd 2.8 3.6 v low-level output voltage v ol r l of 1.425 k ? to 3.6 v 0.0 0.3 v se1 v ose1 0.8 v output signal crossover point voltage v crs 1.3 2.0 v input levels for high-speed: high-speed squelch det ection threshold (differential signal) v hssq 100 150 mv high-speed disconnect detection threshold (differential signal) v hsdsc 525 625 mv high-speed data signaling common mode voltage range v hscm ? 50 + 500 mv high-speed differential input signaling level see figure 3-4 . output levels for high-speed: high-speed idle state v hsoi ? 10 + 10 mv high-speed data signaling high v hsoh 360 440 mv high-speed data signaling low v hsol ? 10 + 10 mv chirp j level (differential signal) v chirpj 700 1100 mv chirp k level (differential signal) v chirpk ? 900 ? 500 mv
data sheet s16265ej4v0ds 18 pd720101 figure 3-1. differential input sensitivity range for low-/full-speed 4.6 ? 1.0 input voltage range (v) differential input voltage range differential output crossover voltage range 0.0 0.2 0.4 0.6 0.8 1.0 1.2 1.4 1.6 1.8 2.0 2.2 2.4 2.6 2.8 3.0 3.2 figure 3-2. full-speed buffer v oh /i oh characteristics for high-speed capable transceiver max. min. ? 80 ? 60 ? 40 ? 20 0 v dd ? 0.3 v out (v) i out (ma) v dd ? 2.3 v dd ? 3.3 v dd ? 0.8 v dd v dd ? 1.3 v dd ? 1.8 v dd ? 2.8 figure 3-3. full-speed buffer v ol /i ol characteristics for high-speed capable transceiver max. min. 80 60 40 20 0 0 0.5 1 1.5 2 2.5 3 v out (v) i out (ma)
data sheet s16265ej4v0ds 19 pd720101 figure 3-4. receiver sensitivity for transceiver at dp/dm 0 v differential + 400 mv differential ? 400 mv differential unit interval level 1 level 2 0% 100% point 5 point 2 point 1 point 3 point 4 point 6 figure 3-5. receiver measurement fixtures vbus d+ d- gnd 15.8 ? + to 50 ? inputs of a high speed differential oscilloscope, or 50 ? outputs of a high speed differential data generator ? 50 ? coax 50 ? coax usb connector nearest device test supply voltage 15.8 ? 143 ? 143 ? pin capacitance parameter symbol condition min. max. unit input capacitance c i v dd = 0 v, t a = 25c 6 8 pf output capacitance c o f c = 1 mhz 10 12 pf i/o capacitance c io unmeasured pins returned to 0 v 10 12 pf pci input pin capacitance c in 8 pf pci clock input pin capacitance c clk 6 8 pf pci idsel input pin capacitance c idsel 8 pf
data sheet s16265ej4v0ds 20 pd720101 power consumption parameter symbol condition typ. (30 mhz x?tal) typ. (48 mhz osc) unit power consumption p wd0-0 device state = d0, all the ports does not connect to any function, and each ohci controller is under usbsuspend and ehci controller is stopped. note1 31.4 10.4 ma p wd0-2 the power consumption under the state without suspend. device state = d0, the number of active ports is 2. note2 full- or low-speed device(s) is (are) on the port. high-speed device(s) is (are) on the port. 53.1 204.6 31.9 204.2 ma ma p wd0-3 the power consumption under the state without suspend. device state = d0, the number of active ports is 3. note2 full- or low-speed device(s) is (are) on the port. high-speed device(s) is (are) on the port. 55.3 253.8 34.2 255.5 ma ma p wd0-4 the power consumption under the state without suspend. device state = d0, the number of active ports is 4. note2 full- or low-speed device(s) is (are) on the port. high-speed device(s) is (are) on the port. 57.4 301.6 36.7 300.1 ma ma p wd0-5 the power consumption under the state without suspend. device state = d0, the number of active ports is 5. note2 full- or low-speed device(s) is (are) on the port. high-speed device(s) is (are) on the port. 59.8 349.1 38.8 345.2 ma ma p wd0_c the power consumption under suspend state during pci clock is stopped by crun0. device state = d0. 30.5 10.4 ma p wd1 device state = d1, analog pll output is stopped. note 3 7.7 10.4 ma p wd2 device state = d2, analog pll output is stopped. note 3 7.7 10.4 ma p wd3h device state = d3 hot , vccrst0 = high, analog pll output is stopped. note 3 7.7 10.4 ma p wd3c device state = d3 cold , vccrst0 = low. note 4 0.03 3.81 ma notes 1. when any device is not connected to all the ports of hc, the power consumption for hc does not depend on the number of active ports. 2. the number of active ports is set by the value of po rt no field in pci configuration space ext register. 3. this is the case when pci bus state is b0. 4. this is the case when pci bus state is b3. remark these are estimated value on windows? xp environment.
data sheet s16265ej4v0ds 21 pd720101 system clock ratings parameter symbol condition min. typ. max. unit clock frequency f clk x?tal ? 500 ppm 30 + 500 ppm mhz oscillator block ? 500 ppm 48 + 500 ppm mhz clock duty cycle t duty 40 50 60 % remarks 1. recommended accuracy of clock frequency is 100 ppm. 2. required accuracy of x?tal or oscillator block is including initial frequency accuracy, the spread of x?tal capacitor loading, supply voltage, temperature, and aging, etc.
data sheet s16265ej4v0ds 22 pd720101 ac characteristics (v dd = 3.0 to 3.6 v, t a = 0 to + 70 c) pci interface block parameter symbol condition min. max. unit pci clock cycle time t cyc 30 ns pci clock pulse, high-level width t high 11 ns pci clock pulse, low-level width t low 11 ns pci clock, rise slew rate s cr 0.2v dd to 0.6v dd 1 4 v/ns pci clock, fall slew rate s cf 0.2v dd to 0.6v dd 1 4 v/ns pci reset active time (vs. power supply stability) t rst 1 ms pci reset active time (vs. clk start) t rst-clk 100 s output float delay time (vs. rst0 ) t rst-off 40 ns pci reset rise slew rate s rr 50 mv/ns pci bus signal output time (vs. pclk ) t val 2 11 ns pci point-to-point signal output time (vs. pclk ) t val (ptp) req0 2 12 ns output delay time (vs. pclk ) t on 2 ns output float delay time (vs. pclk ) t off 28 ns input setup time (vs. pclk ) t su 7 ns point-to-point input setup time (vs. pclk ) t su (ptp) gnt0 10 ns input hold time t h 0 ns
data sheet s16265ej4v0ds 23 pd720101 usb interface block (1/2) parameter symbol conditions min. max. unit low-speed source electrical characteristics rise time (10 to 90%) t lr c l = 200 to 600 pf, r s = 36 ? 75 300 ns fall time (90 to 10%) t lf c l = 200 to 600 pf, r s = 36 ? 75 300 ns differential rise and fall time matching t lrfm (t lr /t lf ) 80 125 % low-speed data rate t ldraths average bit rate 1.49925 1.50075 mbps source jitter total (including frequency tolerance): to next transition for paired transitions t ddj1 t ddj2 ? 25 ? 14 + 25 + 14 ns ns source jitter for differential transition to se0 transition t ldeop ? 40 + 100 ns receiver jitter: to next transition for paired transitions t ujr1 t ujr2 ? 152 ? 200 + 152 + 200 ns ns source se0 interval of eop t leopt 1.25 1.50 s receiver se0 interval of eop t leopr 670 ns width of se0 interval during differential transition t fst 210 ns full-speed source electrical characteristics rise time (10 to 90%) t fr c l = 50 pf, r s = 36 ? 4 20 ns fall time (90 to 10%) t ff c l = 50 pf, r s = 36 ? 4 20 ns differential rise and fall time matching t frfm (t fr /t ff ) 90 111.11 % full-speed data rate t fdraths average bit rate 11.9940 12.0060 mbps frame interval t frame 0.9995 1.0005 ms consecutive frame interval jitter t rfi no clock adjustment 42 ns source jitter total (including frequency tolerance): to next transition for paired transitions t dj1 t dj2 ? 3.5 ? 4.0 + 3.5 + 4.0 ns ns source jitter for differential transition to se0 transition t fdeop ? 2 + 5 ns receiver jitter: to next transition for paired transitions t jr1 t jr2 ? 18.5 ? 9 + 18.5 + 9 ns ns source se0 interval of eop t feopt 160 175 ns receiver se0 interval of eop t feopr 82 ns width of se0 interval during differential transition t fst 14 ns
data sheet s16265ej4v0ds 24 pd720101 (2/2) parameter symbol conditions min. max. unit high-speed source electrical characteristics rise time (10 to 90%) t hsr 500 ps fall time (90 to 10%) t hsf 500 ps driver waveform see figure 3-6 . high-speed data rate t hsdrat 479.760 480.240 mbps microframe interval t hsfram 124.9375 125.0625 s consecutive microframe interval difference t hsrfi 4 high- speed bit times data source jitter see figure 3-6 . receiver jitter tolerance see figure 3-4 . hub event timings time to detect a downstream facing port connect event t dcnn 2.5 2000 s time to detect a disconnect event at a hub?s downstream facing port t ddis 2.0 2.5 s duration of driving resume to a downstream port t drsmdn nominal 20 ms time from detecting downstream resume to rebroadcast t ursm 1.0 ms inter-packet delay for packets traveling in same direction for high-speed t hsipdsd 88 bit times inter-packet delay for packets traveling in opposite direction for high-speed t hsipdod 8 bit times inter-packet delay for root hub response for high-speed t hsrspipd1 192 bit times time for which a chirp j or chirp k must be continuously detected during reset handshake t filt 2.5 s time after end of device chirp k by which hub must start driving first chirp k t wtdch 100 s time for which each individual chirp j or chirp k in the chirp sequence is driven downstream during reset t dchbit 40 60 s time before end of reset by which a hub must end its downstream chirp sequence t dchse0 100 500 s
data sheet s16265ej4v0ds 25 pd720101 figure 3-6. transmit waveform for transceiver at dp/dm 0 v differential + 400 mv differential ? 400 mv differential unit interval level 1 level 2 0% 100% point 4 point 3 point 1 point 2 point 5 point 6 figure 3-7. transmitter measurement fixtures vbus d+ d- gnd 15.8 ? + to 50 ? inputs of a high speed differential oscilloscope, or 50 ? outputs of a high speed differential data generator ? 50 ? coax 50 ? coax usb connector nearest device test supply voltage 15.8 ? 143 ? 143 ?
data sheet s16265ej4v0ds 26 pd720101 3.4 timing diagram pci clock 0.4v dd 0.6v dd 0.2v dd 0.5v dd 0.3v dd 0.4v dd (ptp:min) t cyc t high t low pci reset pclk pwr_good vbbrst0 100 ms (typ.) t rst t rst-off pci signals valid t rst-clk
data sheet s16265ej4v0ds 27 pd720101 pci output timing measurement condition pclk 0.4v dd 0.6v dd 0.2v dd output delay output 0.615v dd (for falling edge) 0.285v dd (for falling edge) t val , t val (ptp) t on t off pci input timing measurement condition pclk 0.4v dd 0.6v dd 0.2v dd input t su , t su (ptp) 0.6v dd 0.2v dd 0.4v dd t h
data sheet s16265ej4v0ds 28 pd720101 usb differential data jitter for full-speed t period differential data lines crossover points consecutive transitions n t period + t xdj1 paired transitions n t period + t xdj2 usb differential-to-eop transition ske w and eop width for low-/full-speed t period differential data lines crossover point crossover point extended source eop width: t feopt t leopt receiver eop width: t feopr t leopr diff. data-to- se0 skew n t period + t xdeop usb receiver jitter tolerance for low-/full-speed differential data lines t period t xjr t xjr1 t xjr2 consecutive transitions n t period + t xjr1 paired transitions n t period + t xjr2
data sheet s16265ej4v0ds 29 pd720101 low-/full-speed disconnect detection d ? /d + d + /d ? v izh (min) v il v ss device disconnected disconnect detected t ddis full-/high-speed device connect detection v ih v ss device connected connect detected d ? d + t dcnn low-speed device connect detection v ih v ss device connected connect detected d + d ? t dcnn
data sheet s16265ej4v0ds 30 pd720101 4. package drawings 108 73 136 109 144 72 37 144-pin plastic lqfp (fine pitch) (20x20) item millimeters note a 22.0 0.2 b 20.0 0.2 c 20.0 0.2 d f 1.25 22.0 0.2 s144gj-50-uen s 1.5 0.1 k 1.0 0.2 l 0.5 0.2 r3 + 4 ? 3 g 1.25 h 0.22 0.05 i 0.08 j 0.5 (t.p.) m 0.17 n 0.08 p 1.4 q 0.10 0.05 + 0.03 ? 0.07 each lead centerline is located within 0.08 mm of its true position (t.p.) at maximum material condition. s s m detail of lead end i j f g h q r p k m l n cd s a b
data sheet s16265ej4v0ds 31 pd720101 14 13 12 11 10 9 8 7 6 5 4 3 2 1 n pmlkjhgfedcba e a b zd ze s a2 a a1 item millimeters d e w a a1 a2 e b x y y1 zd ze 12.00 0.10 12.00 0.10 0.80 0.08 0.10 0.20 0.80 0.80 0.20 0.35 0.06 1.48 0.10 1.13 p144f1-80-ea8 0.50 +0.05 ?.10 144-pin plastic fbga (12x12) s wa s wb y1 s s y e s x bab m ? index mark d
data sheet s16265ej4v0ds 32 pd720101 5. recommended so ldering conditions the pd720101 should be soldered and mounted under the following recommended conditions. for soldering methods and conditions other than those recommended below, contact an nec electronics sales representative. for technical information, see the following website. semiconductor device mount manual (http ://www.necel.com/pkg/en/mount/index.html) pd720101gj-uen: 144-pin plastic lqfp (fine pitch) (20 20) soldering method solder ing conditions symbol infrared reflow package peak temperature: 235c , time: 30 seconds max. (at 210c or higher), count: three times or less exposure limit: 3 days note (after that, prebake at 125c for 10 hours) ir35-103-3 partial heating pin temperature: 300c max., time: 3 seconds max. (per pin row) ? note after opening the dry pack, store it at 25c or less and 65% rh or less for the allowable storage period. pd720101f1-ea8: 144-pin plastic fbga (12 12) soldering method solder ing conditions symbol infrared reflow package peak temperature: 235c , time: 30 seconds max. (at 210c or higher), count: three times or less exposure limit: 7 days note (after that, prebake at 125c for 10 hours) ir35-107-3 note after opening the dry pack, store it at 25c or less and 65% rh or less for the allowable storage period.
data sheet s16265ej4v0ds 33 pd720101 [memo]
data sheet s16265ej4v0ds 34 pd720101 [memo]
data sheet s16265ej4v0ds 35 pd720101 1 2 3 4 voltage application waveform at input pin waveform distortion due to input noise or a reflected wave may cause malfunction. if the input of the cmos device stays in the area between v il (max) and v ih (min) due to noise, etc., the device may malfunction. take care to prevent chattering noise from entering the device when the input level is fixed, and also in the transition period when the input level passes through the area between v il (max) and v ih (min). handling of unused input pins unconnected cmos device inputs can be cause of malfunction. if an input pin is unconnected, it is possible that an internal input level may be generated due to noise, etc., causing malfunction. cmos devices behave differently than bipolar or nmos devices. input levels of cmos devices must be fixed high or low by using pull-up or pull-down circuitry. each unused pin should be connected to v dd or gnd via a resistor if there is a possibility that it will be an output pin. all handling related to unused pins must be judged separately for each device and according to related specifications governing the device. precaution against esd a strong electric field, when exposed to a mos device, can cause destruction of the gate oxide and ultimately degrade the device operation. steps must be taken to stop generation of static electricity as much as possible, and quickly dissipate it when it has occurred. environmental control must be adequate. when it is dry, a humidifier should be used. it is recommended to avoid using insulators that easily build up static electricity. semiconductor devices must be stored and transported in an anti-static container, static shielding bag or conductive material. all test and measurement tools including work benches and floors should be grounded. the operator should be grounded using a wrist strap. semiconductor devices must not be touched with bare hands. similar precautions need to be taken for pw boards with mounted semiconductor devices. status before initialization power-on does not necessarily define the initial status of a mos device. immediately after the power source is turned on, devices with reset functions have not yet been initialized. hence, power-on does not guarantee output pin levels, i/o settings or contents of registers. a device is not initialized until the reset signal is received. a reset operation must be executed immediately after power-on for devices with reset functions. notes for cmos devices purchase of nec electronics l 2 c components conveys a license under the philips l 2 c patent rights to use these components in an l 2 c system, provided that the system conforms to the l 2 c standard specification as defined by philips.
pd720101 usb logo is a trademark of usb implementers forum, inc. windows is either a registered trademark or a trademark of microsoft corporation in the united states and/or other countries. the information in this document is current as of june, 2004. the information is subject to change without notice. for actual design-in, refer to the latest publications of nec electronics data sheets or data books, etc., for the most up-to-date specifications of nec electronics products. not all products and/or types are available in every country. please check with an nec electronics sales representative for availability and additional information. no part of this document may be copied or reproduced in any form or by any means without the prior written consent of nec electronics. nec electronics assumes no responsibility for any errors that may appear in this document. nec electronics does not assume any liability for infringement of patents, copyrights or other intellectual property rights of third parties by or arising from the use of nec electronics products listed in this document or any other liability arising from the use of such products. no license, express, implied or otherwise, is granted under any patents, copyrights or other intellectual property rights of nec electronics or others. descriptions of circuits, software and other related information in this document are provided for illustrative purposes in semiconductor product operation and application examples. the incorporation of these circuits, software and information in the design of a customer's equipment shall be done under the full responsibility of the customer. nec electronics assumes no responsibility for any losses incurred by customers or third parties arising from the use of these circuits, software and information. while nec electronics endeavors to enhance the quality, reliability and safety of nec electronics products, customers agree and acknowledge that the possibility of defects thereof cannot be eliminated entirely. to minimize risks of damage to property or injury (including death) to persons arising from defects in nec electronics products, customers must incorporate sufficient safety measures in their design, such as redundancy, fire-containment and anti-failure features. nec electronics products are classified into the following three quality grades: "standard", "special" and "specific". the "specific" quality grade applies only to nec electronics products developed based on a customer- designated "quality assurance program" for a specific application. the recommended applications of an nec electronics product depend on its quality grade, as indicated below. customers must check the quality grade of each nec electronics product before using it in a particular application. the quality grade of nec electronics products is "standard" unless otherwise expressly specified in nec electronics data sheets or data books, etc. if customers wish to use nec electronics products in applications not intended by nec electronics, they must contact an nec electronics sales representative in advance to determine nec electronics' willingness to support a given application. (note) ? ? ? ? ? ? m8e 02. 11-1 (1) (2) "nec electronics" as used in this statement means nec electronics corporation and also includes its majority-owned subsidiaries. "nec electronics products" means any product developed or manufactured by or for nec electronics (as defined above). computers, office equipment, communications equipment, test and measurement equipment, audio and visual equipment, home electronic appliances, machine tools, personal electronic equipment and industrial robots. transportation equipment (automobiles, trains, ships, etc.), traffic control systems, anti-disaster systems, anti-crime systems, safety equipment and medical equipment (not specifically designed for life support). aircraft, aerospace equipment, submersible repeaters, nuclear reactor control systems, life support systems and medical equipment for life support, etc. "standard": "special": "specific":

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